OPERATING MODES OF 8259A

1.Fully Nested Modes

.Default mode.

.IR0 has the highest priority and IR7 has the lowest one.

.If the ISR (in service) bit is set, all the same or lower priority interrupts are inhibited.

2.End Of Interrupt

.The ISR bit can be reset either with AEOI bit of ICW1 or by EOI command.

.Two types of EOI command;

a)Specific

b)Non-specific

.The non-specific EOI command automatically reset the highest ISR bit.

.When a mode that may disturb the fully nested structure, the specific EOI command is issued to reset a particular ISR bit.

.An ISR bit that is masked by the corresponding IMR bit, will not be cleared by a non-specific EOI , if it is in special mode.

3.Automatic Rotation

.Used in the applications where , all the interrupting devices are of equal priority.

.In this mode, an IR level receives lowest priority after it is served while the next device to be served gets the highest priority in sequence.

4.Automatic EOI Mode

.Till AEOI=1 in ICW4, 8259A operates in AEOI mode.

.The 8259A performs a non- specific EOI at the trailing edge of the last /INTA pulse automatically.

.AEOI should be used only when a nested multilevel interrupt structure is not required.

5.Specific Rotation

.A bottom priority level can be selected, using L2, L1 and L0 inOCW2 and R=1, SL=1,EOI=0.

.The selected bottom priority fixes other priorities.

6.Special Mask Mode

.When a mask bit is set in OCW, it inhibits further interrupts at that level and enables interrupt from other levels, which are not mastered.

7.Edge And Level Triggered Mode

.Decides whether the interrupt should be edge triggered or level triggered.

.If bit LTIM of ICW1=0, they are edge triggered, otherwise level triggered.

8.Readng 8259A Status

.Used to read the , status of the internal registers of 8259A.

.Reading is possible only in no polled mode.

.OCW3, is used to read IRR and ISR and OCW1 for IMR.

9.Poll command

.The INT output is neglected, though it functions normally by not connecting INT output or by masking INT input of the microprocessor.

.This mode is entered by setting p=1 in OCW3.

.A poll command may give more than 64 priority levels.

10.Special Fully Nested Mode

.Used in more complicated systems.

.Similar to, normal nested mode.

.When an interrupt request from a certain slave is in service, this slave can further send requests to the master.

.The master interrupts the CPU only.

11.Buffered Mode

.When the 8259A is used in the system in which bus driving buffers are used on the data buses, the problem of enabling the buffers arises.

.The 8259A sends a buffer enable signal on /SP//EN pin.

12.Cascade Mode

.The slave INT outputs are connected with master IR inputs. When a slave request line is activated and acknowledged, the master will enable the slave to release the vector addresses during the second pulses of /INTA sequence.

.The cascade lines are normally low and contain slave addresses codes from the trailing edge of the first /INTA pulse to the trailing edge of the second /INTA pulse.

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CISC AND RISC

CISC:-

• Acronym for Complex Instruction Set Computer.
• They are chips that are easy to program and which makes efficient use of m/y.
• “High level” instruction set

• Executes several “low level operations”
• Ex: load, arithmetic operation,m/y store.

• Used in most common Intel 80x86 and Motorola 68k series.

FEATURES OF CISC:-

• Extensive instructions.
• Complex and efficient machine instructions.
• Extensive addressing capabilities for m/y operations.
• Microending of the machine instructions.
• Relatively few registers.
• Instruction can operate directly on m/y.
• Small number of general purpose registers.
• Instructions take multiple clock to execute.
• Few lines of code per operation.

CISC ATTRIBUTES:-

The design constraints that led to the development of CISC give CISC instructions set some common characteristics:

• A 2-operand format,where instruction have a source and a destination.

• Register to register,register to m/y,and m/y to register commands.
• Multiple addressing modes for m/y,including specialized modes for indexing through arrays.
• Variable length instructions where length often varies according to the addressing mode.
• Instructions which require multiple clock cycles to execute.

Ex: Pentium is considered a modern CISC processor.

CISC Disadvantages:-

• Instruction set and chip hardware become more complex with each generation of computers,
• as many instructions could be stored in m/y with least possible wasted space,individual instructions could be of alost any length-this means that

different instructions will take different amounts of clock time to execute,slowing down overall performance of the machine.

• Only 20% of the available instructions are used ina typical pgm.

RISC:-

• Reduced Instruction Set Computer
• It is a type of microprocessor architectrure that utilizes a small,highly –optimized set of insrtructions,rather than a more specialized set of instructions often found in other types of architectures.
• Executes a series of simple instructions instead of a complex instruction.
• Incorporates a large number of general registers for arithmetic operations to avoid storing variables on a stack in m/y.
• Only the load and store instructions operate directly onto m/y.
• Pipelining=speed.

• EVOLUTION/HISTORY:-

• The first RISC projects came from IBM,Stanford,and UC-Berkeley in the late 70s.
• Ex:IBM 801,Stanford MIPS, and Berkrts,oreley RISC 1 and 2.

• DESIGN FEATURES:-

• ONE CYCLE EXECUTION TIME:-RISC processors have a CPI(clock per execution)of one cycle.this is due to the optimization of each instruction on the CPU and a technique called pipelining.
• PIPELINING:-A technique that allows for simultaneous execution of parts,or stages,of instructions to more efficiently process instructions.
• Large number of registers:-the RISC design incorporates a larger number of registers to prevent in large amounts of intertactions with m/y.

• ADVANTAGES OF RISC:-

• Being simple,can be hardwired while cisc have to use micro-programming yo implement complex instructions
• Set of simple instrns result in reduced complexity of the cu and datapath,so high clock frequency and high speed.
• m/y management units or floating point arithematic units can be plced in same chip.
• Smaller chips,lowers per-chip cost .
• High- level language compilers produce more efficient codes in a RISCprocessor than CISC.
• Shorter design cycle-RISC processors can be designed,developed and tested more easily than CISC.
• Application programmers find more easy,due to simple instrn set.
  loading and decoding of instrn is simple and fast.decoding is simplified since opcode & adrs fields are located in same position for all instructions.

• RISC ATTRIBUTES:-

• Reduced instruction set.
• Less complex,simple instructions.
• Hardwired control unit and machine instructions.
• Few addressing schemes for m/y operands with only two basic instructions-LOAD and STRORE.
• Many symmetric registers which are organized into a register file.

• BASIC FEATURES OF RISC PROCESSORS:-

• SIMPLE INSTRUCTION SET
• Same length instruction:each instrn is of same length,so can be fetched in single operation.
• Single machine –cycle instrns:so it allows processor to handle many instrns at a time.RISC processors have unity CPI(clk per instrn).
• Pipelining:usually massive pipelining is embedded in RISC processor.pipelining is a key to speed.
• Very few addressing modes and formats.
• Large no of registers:it prevents large amt of interactions withj m/y.
• Microending not required:bcoz simple instrns can be easily built into hardware.
• Load and store architecture:implies that all m/y accesses take place using Load or Store type operations.

• DESIGN ISSUES OF RISC PROCESSORS:-

1).REGISTER WINDOWING:

• Concept involves a mechanism where chips expose 32 registers to the programmer at any one time,but these registers is a window into larger set of physical registers.
• Additional registers are hidden from view until a subroutine is called.
• SPARC processors use this technique.

• DISADVANTAGES:-

• NO OF PHYSICAL REGISTERS is finite,so runs out.

of space.

• Unable to predict whether stack will overflow or under flow ,so performance unpredictable.
• Processor generates asoftware faults,consuming more cycles.
• Enormous demands on mux and register ports.
• Impossible to add multithreading
• Difficult to keep clock cycles.

2).MASSIVE PIPELINING:-

• Five steps:-

1.fetch instrns from m/y

2.read registers and decode instrn.

3.execute instrn or calculate adrs,.

4.access an operand in data m/y.

5.write result to register.

• CAUTIONS ON THE USE OF RISC:

• Code quality should be maintained.
• Scheduling :choose compilers carefully based on quality.
• Debugging:instruction scheduling can make debugging difficult.
• Code expansion
• On chip cache required to feed large instructions.

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DESIGN OF A PC BASED MULTIMICROPROCESSOR SYTEM

Introduction

• Gives an overview of a PC based multimicroprocessor system.
• Designed two subprocessing cards with an 8088 based system &64 memory each.
• These IBM PC compatible cards along with switching logic can be inserted in a PC simultaneously.
• Contain 3 8088 processors with one operating as a master processor while the other two operating in the slave mode.
• Master CPU means the main CPU &slave CPU referred to a subprocessors.
• The job is communicated with the system using the master processor of PC in the form of filenames.
• Master processor checks, if there is any invalid filename in the sequence, if found it accepts the next filename & display the invalid filename
• Both slave processors start executing the program one by one & each slave processor interrupts the main processor to ask for a new job.
• After the execution of each program is over, slave processors store result in respective result memory buffers and master processor store the result in hard disk.
• Hardware design structure describes the design procedure of the module& the details of the subprocessing cards.

Design of the subprocessing units

Design of the address/data separating circuit

• System is built around a PC that has the main processor 8088, acts as a root node/master.
• The main processor & both slave processors address a memory externally interfaced to PC.
• Transreceivers are required to derive the data lines from multiplexed address/data bus the latches are enabled by the ALE signal and the data will be enabled by the DEN signal.DEN signal, combination with DT/R signal decides the direction of data flow.
• ALE, DEN and DT/R are derived by separate 8288 bus controller chip. Since 8088 is used in maximum mode, all control signals are derived by 8288.
• Subprocessors will be able to run only .EXE files. Each subprocessor supports 64K byte memory. There is a constraint that EXE files should not be more than 60K bytes in size. The remaining 4K is reserved for the result buffer of the subprocessor.
• The same 64K memory supported by a slave is interfaced with the CPU of the PC.
• A clock is available at the IO channel of the PC may be used for driving the slave CPUs .There will be the constraint on the slave processors that the maximum speed of their operation can never be more than that of the main CPU.A separate clock generator will add some flexibility of operation and development.
• 64K byte local memory of a subprocessor is to be interfaced such that the subprocessor and the main processor identify a particular location by the same physical address.

Design of the bus window

• Bus window is a part of memory which can be addressed by more than one processor for communication.
• Two slave processors & so there will be two bus windows, one for each. Both windows are addressable by the master processor of PC which is the main processor, but each slave processor can address only one of them.

• The main processor has 64K byte personal memory under 00000 to 9FFFF.The two slots, each of 64K, starting from D0000H to DFFFFH and E0000H to EFFFFH are free. These 64K memory slots can be used as the bus window as well as the local memories for the individual slave CPUs.

To avoid relocation & calculations, identify the memory locations in the window by the same physical addresses for both the processors. This suggests that the memory interfacing logic should be identical for both.

• Main and sub processors able to identify particular location by a single physical address.

Control signals for bus windows

• Here derive read & write control signals for the bus windows.
• As a window is to be written or read by both processors, the MEMR and MEMWR signals of both processors are to be connected to WR and RD pins of memory. A buffer is used for isolating read/write operations of CPU.

Design of isolation between the processors

• When both the processors i.e., slave and master address a common memory, all of their data lines and some of their address lines may be required to be connect with each other.
• When both the CPUs desire to access the common memory concurrently, a conflict may arise due to bus contention among the CPUs .To resolve this conflict, additional hardware is needed which will prevent one processor from referring to the bus window when other processor is using it.
• When one processor is using the bus window, the other one should not be allowed to access the bus, ie. The other processor should not place the address/data on the bus.
• This operation suggests the use of solid state switches .To derive these switches external hardware like address decoders and 8259 I/O cards will be required .The address, data and control lines should be buffered.

Isolation Controllers(Switch Controllers)

1.An 8255 IO Card has been used to control the tristate buffers that provide isolation.

2.When a subprocessor wants to communicate with a bus window,it informs the main processor to disable the tristate buffers.

3.The master C.P.U outputs a '1' bit on the particular pin of the port which is used to drive the chip enable lines of the 74245s which are used for the isolation.

4.Then a reset pin is generated on the another pin of 8255 to reset the slave processor,usin one more OUT instruction,to start the execution.

Interrupt Mechanism

1.As said earlier,the job is transferred to a bus window of a subprocessor for execution.Then a reset pulse is issued to the subprocessor using the OUT operation.

2.The subprocessor starts the execution and when it completes the execution,it shows the halt status on the status lines.

3.From these status lines,a signal is derieved,which interrupts the main processor.

4.The results of execution are next transferred to the master and the slave asks for the next task.

5.After entering the halt state,the status at S_2/,S_1/,S_0/ becomes 011.A signal which is low for all other status and high for the above status is to be generated.A simple 3-input logic will serve the purpose.

6.For any other operation of the processor,the status will be diiferent than that for halt.

7.The o/p of the above given logic,will be high for the above said halt status.

8.Thus, a transition from low to high logic level is achieved,on the interrupt line of P.C.

9.The subprocessor will remain in the halt state,till the main processor allocates it

a new task and resets it 10.After that,it will run the next allocated main task

DERIVING THE REQUIRED CONTROL SIGNAL

• 74245 chips are selected for isolation
• All the 74245s are enabled if the main processor wants to communicate with the bus window
• Signal flow through 74245 is unidirectional
• Enabling or disabling of isolation chips is controlled by isolation driver
• Control line is the RESETIN pin of each 8284A clock generator
• This pin resets when LOGIC 0 is applied to this pin, and the sub processor remains in that state when LOGIC1 is applied to it
• DT/R of PC is not available on the IO channel , it is derived from MEMR and MEMWR signals
• For MEMR operation , the data flows from memory to the CPU, so the isolation buffer is in receiver mode
• For MEMWR operation , data flows from CPU to memory, so the isolation buffer is in transmit mode
• In the diagram of data bus isolation, if DIR pin is high , it enters transmit mode; if it is 0 it enters receive mode
• If the data buffers are enabled at wrong moment then all irrelevant, erratic data present on data bus of the sub processing unit will be placed over the data bus of PC
• Data buffers should be enabled only if any bus window chip is selected
• Main processor sends the isolation control signal through isolation drivers

SYSTEM SOFTWARE DESIGN

System software of the complete system consists of 3 parts:

• Main control program-: controls the total operation of the system

• Two parts are the small local initialisation programs for each sub processors

MAIN PROGRAM DESIGN

• The software for a multiprocessor system should be defined as modular as possible
• Software modules must be used only by a particular processor in its local memory
• The total system is interrupt driven

Complete software is divided into 3 parts:

• MAIN program
• Interrupt routine IRT2 for first sub processing unit
• Interrupt routine IRT3 for second sub processing unit

• The main program accepts the filename inputs at its prompt
• Looks for invalid filename to discard and accepts the next file name
• When sub processer starts execution , the main program makes the master processer to wait for the completion of execution
• Two slave processer use two interrupt inputs of the master to inform it that the previously allotted task is over and the master may read the results and allot them the next task
• Main program consists of two interrupt service routines for the two slaves.
• The functions of them are:

• Store the result of the previous program run by the sub processer
• Select the next program from EXE filename sequence
• Load it to the bus window of that particular sub processer
• Issue run message to the sub processer

• For each of these functions a separate routine is written
• All the routines are linked together to form a complete program
• Each program is checked independently for the passed input parameters
• List of the required inputs to each routine is prepared and checks whether a particular routine prepares the expected output parameters
• This is checked till the complete program run successfully
• Last step is to run the complete program and search for bugs if any and to remove them

MAIN PROGRAM

LOCAL MONITORS

• It contains initialisation routines which initialises the internal registers of the slave processer
• This is for the execution of the allotted task in the local memory
• These programs are available in the local memory and are not accessible to the master

INITIALISATOIN ROUTINE

• When a program is loaded in the bus window of a particular slave processer, the segment registers of that processers should be initialised according to the available local memory

• This routine contains the initialisation of all the segment registers and stack pointers
• After the initialisation of the processer the execution starts from 0200H. This is fixed by the local monitor as the program entry point
• Users program must contain ORG 200H statement at the start of the code segment

Local monitor initialisation program for sub processer1

• Mov AX,0D000H
• Mov DS,AX
• Mov SS,AX
• Mov ES,AX
• Mov SP,0F7FFH
• JMP 0D000:0200H

• For the other sub processer , the same program is used but the segment address of the code and the data segment is 0E000H instead of 0D000H

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INTERFACING I/O PORTS

• I/O ports are devices through which the microprocessor (µP) communicates with other devices or external data sources /destination

INPUT ACTIVITY: The activity that enables the MP to read data from external devices

Eg: keyboard, joystick, mouse

OUTPUT ACTIVITY: Transfers from the MP to the external devices.

Eg: CRT-display, 7-segment display, printers etc.

INPUT DEVICES: Feed data into a MP system

OUTPUT DEVICES: Accept data from a MP system

• That is for MP system i/p activity is similar to read operation & o/p activity is similar to write operations

IORD: Operation is related to reading data from i/p device

IOWR: Writing data to an o/p device

• In programmable devices, the control word & status word can be written & read using i/p & o/p devices.
• After executing OUT operation, the data appears on the data bus at the same time a device signal is generated using address & control signals.
• If the data is to be there, at the o/p of the device till the next change , it must be latched.
• If the o/p port is to be source large currents the port lines must be buffered.
• So the latch acts as a good o/p port Chip 74LS373 contains 8 buffered latches & can be used as an 8 bit o/p port.
• While reading, one should take care that much current should not be sourced or sunk from the data lines to avoid loading.
• To avoid this problem, can use a tristate buffer as an i/p device.
• An i/p port may not be a latch as it reads the status of a signal at a particular instant.
• The chip 74LS245 contains 8 buffers & may be used as an 8 bit i/p port.
• 74LS245: A bidirectional buffer. But using it as an i/p device, only one direction is useful. This direction is selected using DIR pin.
• The OE & CS are the chip selects of 74LS373 & 74LS245 respectively.
• DS & QS are corresponding latch i/ps & o/ps.
• CLK is the clock i/p for D Flip Flop.
• If DIR=1, then direction is from A(i/p) to B(o/p) otherwise the data direction is from B(i/p) to A(o/p)

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STEPS IN INTERFACING AN I/O DEVICE

Steps performed to interface a general I/O device with a CPU

 Connect the data bus of the MP system with the data bus of the I/O port.

 Derive a device address pulse by decoding the required address of the device & use it as the chip select of the device.

 Use a suitable control signal ie, IORD & IOWR to carry out device operations.

METHODS OF INTERFACING I/O DEVICES

Two methods

I/O MAPPED I/O & MEMORY MAPPED I/O

 I/O MAPPED I/O

 Devices are viewed as distinct I/O devices accordingly

 All the available address lines are not used (upto 16 bits are used)

 At most 16/8 lines are used

 Unused higher order bits are set to logic 0

 IN & OUT instructions are used by devices

 Requires less hardware for decoding

 Maximum of 64K I/O devices 32K I/O devices can be interfaced

 IORD &IOWR signals are used for interfacing

 I/O operations are more sluggish

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 MEMORY MAPPED I/O

• Devices are viewed as memory locations & are addressed

• All available address lines are used

• Can have as many as 1MB mapped I/O devices

• Memory locations & memory mapped devices can’t have common address

• MRDC & MRTC are used for interfacing

• Data transfer instructions (MOV, LEA) can be used to communicate with memory mapped I/O devices

• Slower data transfer compared with memory access

• Rarely used

• Memory operations are faster

• Requires complex hardware for decoding

PROBLEM

Interface a i/p port 74LS245 to read the status of switches SW1 to SW8. The switches, when shorted, input a ’1’ else input a ‘0’ to the MP system. Store the status in register BL. The address of the port is 0740h?

ANSWER:

MOV BL ; Clear BL for status

MOV DX, O740H ; 16 bit port address in DX

IN AL, DX ; Read port 0740H for switch positions

MOV BL, AL ; Store status of switches from AL into BL

HLT ; Stop

INSTRUCTION EXECUTION TIMING

Minimum Mode 8086 System

• In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic 1.

• In this mode, all the control signals are given out by the microprocessor chip itself. There is a single microprocessor in the minimum mode system.

• The remaining components in the system are latches, transceivers, clock generator, memory and I/O devices.

Some type of chip selection logic may be required for selecting memory or I/O devices, depending upon the address map of the system.

• The clock generator generates the clock from the crystal oscillator and then shapes it and divides to make it more precise so that it can be used as an accurate timing reference for the system.

• The clock generator also synchronizes some external signal with the system clock.

• The working of the minimum mode configuration system can be better described in terms of the timing diagrams rather than qualitatively describing the operations.

• The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in two parts, the first is the timing diagram for read cycle and the second is the

timing diagram for write cycle

The read cycle begins in T1 with the assertion of address

latch enable (ALE) signal and also M / IO signal. During

the negative going edge of this signal, the valid address is

latched on the local bus.

• The BHE and A0 signals address low, high or both bytes.

From T1 to T4, the M/IO signal indicates a memory or I/O operation.

• At T2, the address is removed from the local bus and is

sent to the output. The bus is then tristated. The read (RD)

control signal is also activated in T2

• The read (RD) signal causes the address device to enable

its data bus drivers. After RD goes low, the valid data is available on the data bus.

• A write cycle also begins with the assertion of ALE and

the emission of the address. The M/IO signal is again

asserted to indicate a memory or I/O operation. In T2, after sending the address in T1

the processor sends the data to be written to the addressed location.

Maximum Mode 8086 System

• In the maximum mode, the 8086 is operated by strapping

the MN/MX pin to ground.

• In this mode, the processor derives the status signal S2, S1,S0.

Another chip called bus controller derives the control

signal using this status information .

• In the maximum mode, there may be more than one

microprocessor in the system configuration.

• The components in the system are same as in the minimum

mode system.

• Here the only difference between in timing diagram

between minimum mode and maximum mode is the status

signals used and the available control and advanced

command signals.

• R0, S1, S2 are set at the beginning of bus cycle.8288 bus

controller will output a pulse as on the ALE and apply a

required signal to its DT / R pin during T1.

• In T2, 8288 will set DEN=1 thus enabling transceivers, and

for an input it will activate MRDC or IORC. These signals are activated until T4.

For an output, the AMWC or AIOWC is activated from T2to T4

and MWTC or IOWC is activated from T3to T4.

• The status bit S0 to S2 remains active until T3 and become passive during T3 and T4.

• If reader input is not activated before T3, wait state will be inserted between T3 and T4.

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INSTRUCTION EXECUTION TIMING

Minimum Mode 8086 System

• In a minimum mode 8086 system, the microprocessor

8086 is operated in minimum mode by strapping its

MN/MX pin to logic 1.

• In this mode, all the control signals are given out by the

microprocessor chip itself. There is a single

microprocessor in the minimum mode system.

• The remaining components in the system are latches,

transreceivers, clock generator, memory and I/O devices.

Some type of chip selection logic may be required for

selecting memory or I/O devices, depending upon the

address map of the system.

• The clock generator generates the clock from the crystal

oscillator and then shapes it and divides to make it more

precise so that it can be used as an accurate timing

reference for the system.

• The clock generator also synchronizes some external signal

with the system clock.

• The working of the minimum mode configuration system

can be better described in terms of the timing diagrams

rather than qualitatively describing the operations.

• The opcode fetch and read cycles are similar. Hence the

timing diagram can be categorized in two parts, the first is

the timing diagram for read cycle and the second is the

timing diagram for write cycle

The read cycle begins in T1 with the assertion of address

latch enable (ALE) signal and also M / IO signal. During

the negative going edge of this signal, the valid address is

latched on the local bus.

• The BHE and A0 signals address low, high or both bytes.

From T1 to T4, the M/IO signal indicates a memory or I/O operation.

• At T2, the address is removed from the local bus and is

sent to the output. The bus is then tristated. The read (RD)

control signal is also activated in T2

• The read (RD) signal causes the address device to enable

its data bus drivers. After RD goes low, the valid data is available on the data bus.

• A write cycle also begins with the assertion of ALE and

the emission of the address. The M/IO signal is again

asserted to indicate a memory or I/O operation. In T2, after sending the address in T1

the processor sends the data to be written to the addressed location.

Maximum Mode 8086 System

• In the maximum mode, the 8086 is operated by strapping

the MN/MX pin to ground.

• In this mode, the processor derives the status signal S2, S1,S0.

Another chip called bus controller derives the control

signal using this status information .

• In the maximum mode, there may be more than one

microprocessor in the system configuration.

• The components in the system are same as in the minimum

mode system.

• Here the only difference between in timing diagram

between minimum mode and maximum mode is the status

signals used and the available control and advanced

command signals.

• R0, S1, S2 are set at the beginning of bus cycle.8288 bus

controller will output a pulse as on the ALE and apply a

required signal to its DT / R pin during T1.

• In T2, 8288 will set DEN=1 thus enabling transceivers, and

for an input it will activate MRDC or IORC. These signals are activated until T4.

For an output, the AMWC or AIOWC is activated from T2to T4

and MWTC or IOWC is activated from T3to T4.

• The status bit S0 to S2 remains active until T3 and become passive during T3 and T4.

• If reader input is not activated before T3, wait state will be inserted between T3 and T4.

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8086 Instruction Set Summary

The following is a brief summary of the 8086 instruction set:

1. Data copy/transfer Instructions

These type of instruction are used to transfer data from source operand to destination operand. All the store, move, load, exchange, input and output instructions belong to this category.

a) Memory/Register Transfers

LDS Load pointer using data segment

LES Load pointer using extra segment

MOV Move byte or word to register or memory

XCHG Exchange byte or word

XLAT Translate byte using look-up table

b) Stack Transfers

PUSH Push data onto stack

PUSHF Push flags onto stack

POP Pop data onto stack

POPF Pop flags off stack

c) AH/Flags Transfers

LAHF Load AH from flags

SAHF Store AH into flags

d) Address Transfer

LEA Load effective address

2. Arithmetic & Logical Instructions

All the instruction performing arithmetic, logical, increment, decrement, compare and scan instructions belong to this category.

a) Addition

ADD Add byte or word

AAA ASCII adjust for addition

INC Increment byte or word

b) Subtraction

SUB Subtract byte or word

AAS ASCII adjust for subtraction

DEC Decrement byte or word

c) Multiplication

MUL Multiply byte or word (unsigned)

IMUL Integer multiply byte or word (signed)

AAM ASCII adjust for multiplication

d) Division

DIV Divide byte or word (unsigned)

IDIV Integer divide byte or word (signed)

AAD ASCII adjust for division

e) Conversion

CBW Convert byte to word

CWB Convert word to byte

f) Logical

AND Logical AND of byte or word

OR Logical OR of byte or word

NOT Logical NOT of byte or word (one's complement)

XOR Boolean exclusive OR

TEST Test byte or word (AND without storing)

3. Branch Instructions

These instructions transfer control of execution to the specified address.

All the call, jump, interrupt and return instruction belong to this class.

a) Unconditional Transfers

CALL Call for procedure

RET Return from procedure

JMP Unconditional jump

INT Software interrupt

IRET Return from interrupt

b) Conditional Transfers

JA (JNBE) Jump if above (not below or equal)

JAE (JNB) Jump if above or equal (not below)

JB (JNAE) Jump if below (not above or equal)

JBE (JNA) Jump if below or equal (not above)

JE (JZ) Jump if equal (zero)

JG (JNLE) Jump if greater (not less or equal)

JGE (JNL) Jump if greater or equal (not less)

JL (JNGE) Jump if less (not greater nor equal)

JLE (JNG) Jump if less or equal (not greater)

JCXZ Jump if CX equals zero

4. Loop Instructions

If these instructions have REP prefix with CX used as count register, they can be used to implement unconditional and coditional loops. The LOOP, LOOPNZ and LOOPZ instructions belong to this category.

LOOP Loop unconditional, count in CX

LOOPE Loop if equal (zero), count in CX

LOOPNE Loop if not equal (not zero), count in CX

5. Machine Control Instructions

These instructions control the machine status. NOP, HLT, WAIT and LOCK instructions belong to this class.

HLT Halt processor

LOCK Lock bus during next instruction

NOP No operation (do nothing)

WAIT Wait for signal on TEST input

ESC Escape to external processor interface

6. Flag Manipulation Instructions

All the instructions which directly affect the flag register, come under this group of instruction. Instructions like CLD, STD, CLI, STI, etc. belong to this category of instructions.

CLC Clear Carry Flag

CMC Compliment Carry Flag

STC Set Carry Flag

CLD Clear Direction Flag

STD Set Direction Flag

CLI Clear Interrupt Enable Flag

STI Set Interrupt Enable Flag

7. Shift & Rotate Instructions

These instructions involve the bitwise shifting or rotation in either direction with or without a count in CX.

SAL Arithmetic shift left byte or word by 1 or CL

SAR Arithmetic shift right byte or word by 1 or CL

SHL Logical shift left byte or word by 1 or CL

SHR Logical shift right byte or word by 1 or CL

RCL Rotate left through carry byte or word by 1 or CL

RCR Rotate right through carry byte or word by 1 or CL

ROL Rotate left byte or word by 1 or CL

ROR Rotate right byte or word by 1 or CL

8. String Instructions

These instructions involve various string manipulation operations like load, move, scan, compare, store, etc. These instructions are only to be operate upon the strings.

CMPSB Compare string of bytes

CMPSW Compare string of words

LODSB Load string of bytes

LODSW Load string of words

MOVSB Move string of bytes

MOVSW Move string of words

SCASB Scan string of bytes

SCASW Scan string of words

STOSB Store string of bytes

STOSW Store string of words

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The 8086 Addressing Modes

- 8086 memory addressing modes provide flexible access to memory, allowing you to easily access variables, arrays, records, pointers, and other complex data types.

-12 addressing modes classified in 5 groups

i ) Addressing modes for register and immediate data

1. Register addressing

-the instruction will specify the name of the register which holds the data to be operated by the instruction

-ex: MOV CL, DH : content of 8-bit DH register is moved to another 8-bit register CL

2. Immediate addressing

-an 8-bit or 16-bit data is specified as a part of the instruction

-ex: MOV DL, 08H : The 8-bit data (08H) given in the instruction is moved to DL register

ii) Addressing modes for memory data

3. Direct addressing

-an unsigned 16-bit displacement or signed 8-bit displacement will be specified in the instruction

-ex: MOV DX, [08H]

EA=0008H (sign extended 8-bit displacement)

BA= (DS)*16; MA=BA+EA

(DX)<= (MA) OR DL<= (MA)

DH<= (MA+1)

4. Register indirect addressing

-the name of the register which holds the effective address will be specified in the instruction

-ex: MOV CX, [BX]

5. Based addressing

-BX or BP register is used to hold a base value for effective address and a signed 8-bit or unsigned 16-bit displacement will be specified in the instruction

-ex: MOV AX, [BX+08H]

6. Indexed addressing

-SI or DI reg. is used to hold an index value for memory data and a signed 8-bit displacement or unsigned 16-bit displacement will be specified in the instruction

-ex: MOV CX,[SI+0A2H]

7. Based index addressing

-the EA is given by the sum of base value and 8-bit or 16-bit displacement specified in the instruction

-ex: MOV DX,[BX+SI+0AH]

8. String addressing

-for string instructions

-EA of source data is stored in SI reg. and the EA of destination data is stored in DI reg.

iii) Addressing modes for I/O ports

9. Direct I/O port addressing

-used to access data from standard I/O mapped devices or ports.

-ex: IN AL, [09H]: the content of port with address 09H is moved to AL

10. Indirect I/O port addressing

-is used to access data from standard I/O mapped devices or ports and the instruction will specify the name of the register which holds the port address.

-ex: OUT [DX], AX : the content of AX is moved to port whose address is specified by DX

iv) Relative addressing modes

11. Relative addressing

-EA of the pgm instruction is specified relative to IP by an 8-bit displacement

-ex: JZ 0AH

v) Implied addressing modes

12. Implied addressing

-in this the instruction itself will specify the data to be operated by the instruction

-ex: CLC: clear carry

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