Architecture of 8087

• Divided into two sections internally Control Unit(CU) & Numeric Extension Unit (NEU)
• NEU execute all the numeric processor instructions
• CU receives, read & write memory operands & executes the 8087 control instructions
• These two units works asynchronously with each other
• CU responsible for communication b/w CPU & Memory also co-coordinating the Internal Coprocessor execution.
• CU internally maintains a parallel queue, identical to status queue of main CPU
• CU automatically monitors BHE/S7 line to detect CPU type
• 8087 uses QS0 & QS1 pins to obtain & identify the instruction fetched by the host CPU
• Identifies coprocessor  instructions using ESCAPE code bits
• Once CPU recognize ESCAPE code, it triggers the execution of the numeric processor instruction in 8087
• While executing ESCAPE code identifies the coprocessor instruction that requires memory operand & also one does not require any memory operands
• If instruction requires memory operand to be fetched from memory, then the physical address of the operand is calculated using any one of the addressing modes allowed in 8086 & a dummy read cycle is initiated by CPU
• If the CPU does not require any memory operand , it directly executed.
• 8087 is ready with execution results, CU gets the control of bus from 8086 &executes a write cycle to write the results in the memory at the prespecialised address
• NEU execute all instructions including arithmetic, logical 68 bit fraction 15 bit exponent & a sign bit
• When NEU begins by it , the CPU recognize that  the instruction execution not yet complete .This make 8086 wait till the busy pin of 8087.
• TEST input pin of  8086 goes low.
• Microcode control unit generate control signals required for execution of the instruction
• Programmable shifter responsible for shifting the operands during the execution of instructions like FMUL & FDIV

                         SIGNAL DESCRIPTIONS OF 8087

·        AD₀ –AD₅  :- Time multiplexed address/data lines. These lines carry address during T₁   & data during T _{2 ,} T_3, T_W& T₄  states. A₀ used when transfer is an lower byte(D₀-D₇) of data bus, to derive chip select. These act as input lines for CPU driven bus cycle.

·        A₁₉/S₆-A₁₆/S₃ :- Time multiplexed address/status lines.

1.      These functions are similar to the pins of 8086

2.      S₆,S₄ & S₃ are permanently high , S₅ permanently low.

·        BHE/S₇  :-During T₁ BHE/S₇  pin used to  enable data on the higher byte of 8086 data bus .During  T _{2 ,} T_3, T_W& T₄  status line S₇

·        QS₁-QS₀ :- Queue status i/p signal, enable 8087 to keep track of prefetch status of the CPU.

  Status of these lines is decoded as:-

QS1	QS0	Queue status
0	0	No Operation
0	1	First byte of opcode from queue
1	0	Empty queue
1	1	Subsequent byte from queue

                          PIN DIAGRAM OF 8087

·        INT:- Interrupt output used to indicate unmasked exception has been received                    during  execution                              

·        BUSY:-o/p signal ,When high ,indicates instruction.

·        READY:- i/p signal used to inform the coprocessor that the addressed device will complete the data transfer from its side & the bus is likely to be free for the next cycle

·        RESET:- i/p Signal used to abandon the internal activities of coprocessor & prepare it for further execution

·        CLK:-Provide CLK input

·        VCC:-Supply +5 V

·        GND :-Power supply

·        S₂ ,S₁ & S₀ :- 8087 driven or externally driven by CPU.

If these are driven by 8087

S2	S1	S0	Queue status
0	X	X	Unused
1	0	0	Unused
1	0	1	Memory Read
1	1	0	Memory Write
1	1	1	Passive

·        RG/GT_6:-Request/Grant pin used to gain control of bus from host 8086/8088 for operand transfer.

·        An active low pulse of one clock duration generated for the host to inform it that it wants to gain control of the local bus either for itself or for other Co processor connected to RQ/GT Pin.

·        RQ/GT_1:- Bidirectional pin used by other bus masters to convey their need of local bus access to 8087.

         REGISTER SET OF 8087

·        Set of 8 bit registers

·        Used either as a stack or a set of general registers

·        When operating as a stack, it operates from the top on one or two registers

·        While operating as a register set used only with the instruction designed for them.

·        Divided into three

1.      Sign(1 bit)

2.      Exponent(15 bits)

3.      Significant(64 bits)

·        Two bit tag field to indicate the status of contents

·        Instruction may address data registers either implicitly or explicitly

·                    An internal status register field Top is used to address any one of the eight  registers   implicitly. While explicitly addressing the registers, They may be addressed relative to Top.

STATUS WORD OF 8087

15                                                                                                                                                                            0

TAG (7)

TAG(6)

TAG (5)

TAG (4)

TAG (3)

TAG (2)

TAG (1)

TAG (0)

TAG VALUES

00=VALID            01=ZERO

10=SPECIAL       11=EMPTY

• B₀- B₅ :- Indicate that an exception has been deleted
• B₇ :- bit set if any unmasked exception has been detected otherwise cleared
• B₁₂ – B₁₄  :-3 bits are used as the current top of the stack pointer to any of these eight registers.
• B_{6 –} B₁₀& B₁₄   :- 4 condition code bits reflects as status of the results calculated by 8087
• B₁₅   :- Busy bit shows the status NEU B₁₄ =1, NEU is busy with execution otherwise free.

CONDITION CODE TABLE

Instruction type	C3	C2	C1	C0	Interpretation
compare test	0	0	X	0	ST>Source  or 0(FTST)
	0	0	X	1	ST>Source  or 0(FTST
	0	0	X	0	ST>Source  or 0(FTST
Remainder	1	0	X	1	Complete reduction with three low bits of quotient incomplete reduction
	Q1	0	Q0	Q2
Examine	U	1	U	U	Valid, positive un normalized
	0	0	0	0	Invalid,positive, exponent=0
	0	0	0	1	Valid, negative, un normalized
	0	0	1	0	Valid, negative , exponent=0
	0	0	1	1	Invalid, positive, normalized
	0	1	0	0	Valid, positive, normalized
	0	1	0	1	Infinity, positive
	0	1	1	0	Valid, negative, normalized
	0	1	1	1	Infinity, negative
	1	0	0	0	Zero, positive
	1	0	0	1	Empty
	1	0	1	0	Zero, negative
	1	0	1	1	Empty
	1	1	0	0	Invalid, positive, exponent=0
	1	1	0	1	Empty
	1	1	1	0	Invalid, Negative, exponent=0
	1	1	1	1	Empty

• Instruction & Data pointer: - Used to enable the programmers to write their own exception handling subroutines. Before executing a mathematical instruction, the 8087 forms a table in memory containing the instruction address in the field of instruction, operand address in the field of data pointer TAG word Status word , Control word in their respective fields table

  CONTROL WORD REGISTER

• Allows the programmer to select the required processing options out of available once
• 16 – bit control word register is used to control the operation of 8087
• B₀- B₅ used for masking the different

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Interfacing of 8087 Math Co Processor

    

                                                                                                                                          __                                                                                                                                  

·         8087 can be connected with CPU only in max.mode,i.e wen MN/MX pin is grounded.

·         In max. mode, all control signals are derived using a bus controller.

·         Multiplexed address-data bus lines are connected directly from the 8086 to 8087.

·         The status lines and the queue status lines connected directly from 8086 to 8087.

·         The QS0 and QS1 lines may be directly connected to corresponding pins in case of 8086/88 based systems.

·         The Request/Grant signal RQ/GT0 of 8087 is connected to

___ __

RQ/GT1 of 8086.

·         The clock pin of 8087 connected with CPU 8086/88 clock i/p.

·         The interrupt o/p of 8087 is routed to 8086/88 via a programmable interrupt controller.

·                                       ____                                                                                                            

·         The pins AD0-AD15,BHE/S7,RESET,A19/S6-A16/S3 r connected  to corresponding pins of 8086

            ______

·         BUSY signal 8087 is connected to TEST pin of 8086.

·         Interrupt o/p INT of the 8087 to NMI input of 8086. This intimates an error

condition. ______

·         A WAIT instruction is passed to keep looking at its TEST pin, until it finds pin Low to

indicates that the 8087 has completed the computation.

·         SYNCHRONIZATION must be established between the processor and coprocessor in

two situations.

a) The execution of an ESC instruction that require the participation of the NUE

must not be initiated if the NUE has not completed the execution of the previous

instruction.

b) When a processor instruction accesses a memory location that is an operand of

a previous co processor instruction .In this case CPU must synchronize with NPX to

ensure that it has completed its instruction.

Processor WAIT instruction is provided.

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SEGMENT REGISTERS

• Unlike 8085, the 8086 addresses a segmented memory.
• The complete 1 megabyte memory, which the 8086 addresses is divided into 16 logical segments.
• Each segment thus contains 64 Kbytes of memory.
• There are four segment registers

                1.Code Segment  Register(CS)
                2.Data Segment Register(DS)
                3.Extra Segment Regiser(ES)
                4.Stack Segment Register(SS)

• The code segment register is used for addressing a memory location in the code segment of the memory,where the executable program is stored.
• Similarly the data segment register points to the data segment of the memory.
• Thus, the extra segment is also contains data.
• The stack segment register is used for storing stack segment of the memory that is memory which is used for storing stack data.
• The 'CPU' uses the stack for temporarily storing important data, eg: the content of the CPU register which will be required at a later stage.
• The stack grows down, that is the data is pushed onto the stack in the memory locations with decreasing addresses.
• When this information will be required by the CPU.they will be popped of from the stack.
• While addressing any location in the memory bank, the physical address is calculated from two parts, the first is segment address and the second is offset.
• The segment register contain 16-bit segment base addresses related to different segments.
• Any of the pointers and index registers or BX may contain the offset of the location to be addressed.
• The advantage of the scheme is that instead of maintaining a 20-bit register for a physical address.
• The processor just maintains two 16 -bit registers which are within the word length capacity of the machine.
• Thus CS, DS, SS and ES segment registers respectively, segment address for the code , data, stack and extra segments of memory.
• It may be noted that all these segments are the logical segments .they my or may not be physically separated.
• In other words ,a single segment may require more than one memory chip or more than one segment may be accommodated in a single memory chip.

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CS 405 Automata Languages and Computation (2006 Scheme)

(Theory of Computation / Formal Languages and Automata Theory)

Best Text Book in Market :

Introduction to Automata Theory, Languages, and  Computation : John E. Hopcroft, Jeffrey D. Ullman
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