SEGMENT REGISTERS

• Unlike 8085, the 8086 addresses a segmented memory.
• The complete 1 megabyte memory, which the 8086 addresses is divided into 16 logical segments.
• Each segment thus contains 64 Kbytes of memory.
• There are four segment registers

                1.Code Segment  Register(CS)
                2.Data Segment Register(DS)
                3.Extra Segment Regiser(ES)
                4.Stack Segment Register(SS)

• The code segment register is used for addressing a memory location in the code segment of the memory,where the executable program is stored.
• Similarly the data segment register points to the data segment of the memory.
• Thus, the extra segment is also contains data.
• The stack segment register is used for storing stack segment of the memory that is memory which is used for storing stack data.
• The 'CPU' uses the stack for temporarily storing important data, eg: the content of the CPU register which will be required at a later stage.
• The stack grows down, that is the data is pushed onto the stack in the memory locations with decreasing addresses.
• When this information will be required by the CPU.they will be popped of from the stack.
• While addressing any location in the memory bank, the physical address is calculated from two parts, the first is segment address and the second is offset.
• The segment register contain 16-bit segment base addresses related to different segments.
• Any of the pointers and index registers or BX may contain the offset of the location to be addressed.
• The advantage of the scheme is that instead of maintaining a 20-bit register for a physical address.
• The processor just maintains two 16 -bit registers which are within the word length capacity of the machine.
• Thus CS, DS, SS and ES segment registers respectively, segment address for the code , data, stack and extra segments of memory.
• It may be noted that all these segments are the logical segments .they my or may not be physically separated.
• In other words ,a single segment may require more than one memory chip or more than one segment may be accommodated in a single memory chip.

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CS 405 Automata Languages and Computation (2006 Scheme)

(Theory of Computation / Formal Languages and Automata Theory)

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