Steps
performed to interface a general I/O device with a CPU
Connect
the data bus of the MP system with the data bus of the I/O port.
Derive
a device address pulse by decoding the required address of the device
& use it as the chip select of the device.
Use
a suitable control signal ie, IORD & IOWR to carry out device
operations.
METHODS
OF INTERFACING I/O DEVICES
Two
methods
I/O
MAPPED I/O & MEMORY MAPPED I/O
I/O MAPPED I/O
Devices
are viewed as distinct I/O devices accordingly
All
the available address lines are not used (upto 16 bits are used)
At
most 16/8 lines are used
Unused
higher order bits are set to logic 0
IN
& OUT instructions are used by devices
Requires
less hardware for decoding
Maximum
of 64K I/O devices 32K I/O devices can be interfaced
IORD
&IOWR signals are used for interfacing
I/O
operations are more sluggish
________________________________________
MEMORY
MAPPED I/O
• Devices
are viewed as memory locations & are addressed
• All
available address lines are used
• Can
have as many as 1MB mapped I/O devices
• Memory
locations & memory mapped devices can’t have common address
•
MRDC
& MRTC are used for interfacing
•
Data
transfer instructions (MOV, LEA) can be used to communicate with
memory mapped I/O devices
• Slower
data transfer compared with memory access
•
Rarely
used
• Memory
operations are faster
• Requires
complex hardware for decoding
PROBLEM
Interface
a i/p
port 74LS245 to read the status of switches SW1 to SW8. The switches,
when shorted, input a ’1’ else input a ‘0’ to the MP system.
Store the status in register BL. The address of the port is 0740h?
ANSWER:
MOV
BL ; Clear BL for status
MOV
DX, O740H ; 16 bit port address in DX
IN
AL, DX ; Read port 0740H for switch
positions
MOV
BL, AL ; Store status of switches from AL into
BL
HLT
; Stop
INSTRUCTION
EXECUTION TIMING
Minimum
Mode 8086 System
•
In
a minimum mode 8086 system, the microprocessor 8086 is operated in
minimum mode by strapping its MN/MX pin to logic 1.
• In
this mode, all the control signals are given out by the
microprocessor chip itself. There is a single microprocessor in the
minimum mode system.
•
The
remaining components in the system are latches, transceivers, clock
generator, memory and I/O devices.
Some
type of chip selection logic may be required for selecting memory or
I/O devices, depending upon the address map of the system.
• The
clock generator generates the clock from the crystal oscillator and
then shapes it and divides to make it more precise so that it can be
used as an accurate timing reference for the system.
• The
clock
generator also synchronizes some external signal with the
system clock.
• The
working of the minimum mode configuration system can be better
described in terms of the timing diagrams rather than qualitatively
describing the operations.
• The
opcode fetch and read cycles are similar. Hence the timing diagram
can be categorized in two parts, the first is the timing diagram for
read cycle and the second is the
timing
diagram for write cycle
The
read cycle begins in T1 with the assertion of address
latch
enable (ALE) signal and also M / IO signal. During
the
negative going edge of this signal, the valid address is
latched
on the local bus.
• The
BHE and A0 signals address low, high or both bytes.
From
T1 to T4, the M/IO signal indicates a memory or I/O operation.
• At
T2, the address is removed from the local bus and is
sent
to the output. The bus is then tristated. The read (RD)
control
signal is also activated in T2
• The
read (RD) signal causes the address device to enable
its
data bus drivers. After RD goes low, the valid data is available on
the data bus.
• A
write cycle also begins with the assertion of ALE and
the
emission of the address. The M/IO signal is again
asserted
to indicate a memory or I/O operation. In T2, after sending the
address in T1
the
processor sends the data to be written to the addressed location.
Maximum
Mode
8086 System
• In
the maximum mode, the 8086 is operated by strapping
the
MN/MX pin to ground.
•
In
this mode, the processor derives the status signal S2, S1,S0.
Another
chip
called bus controller derives the control
signal
using this status information .
• In
the maximum mode, there may be more than one
microprocessor
in the system configuration.
• The
components in the system are same as in the minimum
mode
system.
• Here
the only difference between in timing diagram
between
minimum mode and maximum mode is the status
signals
used and the available control and advanced
command
signals.
• R0,
S1, S2 are set at the beginning of bus cycle.8288 bus
controller
will output a pulse as on the ALE and apply a
required
signal to its DT / R pin during T1.
• In
T2, 8288 will set DEN=1 thus enabling transceivers, and
for
an input it will activate MRDC or IORC. These signals are activated
until T4.
For
an output, the AMWC or AIOWC is activated from T2to T4
and
MWTC or IOWC is activated from T3to T4.
• The
status bit S0 to S2 remains active until T3 and become passive during
T3 and T4.
• If
reader input is not activated before T3, wait state will be inserted
between T3 and T4.
0 comments:
Post a Comment