CISC AND RISC

CISC:-

• Acronym for Complex Instruction Set Computer.
• They are chips that are easy to program and which makes efficient use of m/y.
• “High level” instruction set

• Executes several “low level operations”
• Ex: load, arithmetic operation,m/y store.

• Used in most common Intel 80x86 and Motorola 68k series.

FEATURES OF CISC:-

• Extensive instructions.
• Complex and efficient machine instructions.
• Extensive addressing capabilities for m/y operations.
• Microending of the machine instructions.
• Relatively few registers.
• Instruction can operate directly on m/y.
• Small number of general purpose registers.
• Instructions take multiple clock to execute.
• Few lines of code per operation.

CISC ATTRIBUTES:-

The design constraints that led to the development of CISC give CISC instructions set some common characteristics:

• A 2-operand format,where instruction have a source and a destination.

• Register to register,register to m/y,and m/y to register commands.
• Multiple addressing modes for m/y,including specialized modes for indexing through arrays.
• Variable length instructions where length often varies according to the addressing mode.
• Instructions which require multiple clock cycles to execute.

Ex: Pentium is considered a modern CISC processor.

CISC Disadvantages:-

• Instruction set and chip hardware become more complex with each generation of computers,
• as many instructions could be stored in m/y with least possible wasted space,individual instructions could be of alost any length-this means that

different instructions will take different amounts of clock time to execute,slowing down overall performance of the machine.

• Only 20% of the available instructions are used ina typical pgm.

RISC:-

• Reduced Instruction Set Computer
• It is a type of microprocessor architectrure that utilizes a small,highly –optimized set of insrtructions,rather than a more specialized set of instructions often found in other types of architectures.
• Executes a series of simple instructions instead of a complex instruction.
• Incorporates a large number of general registers for arithmetic operations to avoid storing variables on a stack in m/y.
• Only the load and store instructions operate directly onto m/y.
• Pipelining=speed.

• EVOLUTION/HISTORY:-

• The first RISC projects came from IBM,Stanford,and UC-Berkeley in the late 70s.
• Ex:IBM 801,Stanford MIPS, and Berkrts,oreley RISC 1 and 2.

• DESIGN FEATURES:-

• ONE CYCLE EXECUTION TIME:-RISC processors have a CPI(clock per execution)of one cycle.this is due to the optimization of each instruction on the CPU and a technique called pipelining.
• PIPELINING:-A technique that allows for simultaneous execution of parts,or stages,of instructions to more efficiently process instructions.
• Large number of registers:-the RISC design incorporates a larger number of registers to prevent in large amounts of intertactions with m/y.

• ADVANTAGES OF RISC:-

• Being simple,can be hardwired while cisc have to use micro-programming yo implement complex instructions
• Set of simple instrns result in reduced complexity of the cu and datapath,so high clock frequency and high speed.
• m/y management units or floating point arithematic units can be plced in same chip.
• Smaller chips,lowers per-chip cost .
• High- level language compilers produce more efficient codes in a RISCprocessor than CISC.
• Shorter design cycle-RISC processors can be designed,developed and tested more easily than CISC.
• Application programmers find more easy,due to simple instrn set.
  loading and decoding of instrn is simple and fast.decoding is simplified since opcode & adrs fields are located in same position for all instructions.

• RISC ATTRIBUTES:-

• Reduced instruction set.
• Less complex,simple instructions.
• Hardwired control unit and machine instructions.
• Few addressing schemes for m/y operands with only two basic instructions-LOAD and STRORE.
• Many symmetric registers which are organized into a register file.

• BASIC FEATURES OF RISC PROCESSORS:-

• SIMPLE INSTRUCTION SET
• Same length instruction:each instrn is of same length,so can be fetched in single operation.
• Single machine –cycle instrns:so it allows processor to handle many instrns at a time.RISC processors have unity CPI(clk per instrn).
• Pipelining:usually massive pipelining is embedded in RISC processor.pipelining is a key to speed.
• Very few addressing modes and formats.
• Large no of registers:it prevents large amt of interactions withj m/y.
• Microending not required:bcoz simple instrns can be easily built into hardware.
• Load and store architecture:implies that all m/y accesses take place using Load or Store type operations.

• DESIGN ISSUES OF RISC PROCESSORS:-

1).REGISTER WINDOWING:

• Concept involves a mechanism where chips expose 32 registers to the programmer at any one time,but these registers is a window into larger set of physical registers.
• Additional registers are hidden from view until a subroutine is called.
• SPARC processors use this technique.

• DISADVANTAGES:-

• NO OF PHYSICAL REGISTERS is finite,so runs out.

of space.

• Unable to predict whether stack will overflow or under flow ,so performance unpredictable.
• Processor generates asoftware faults,consuming more cycles.
• Enormous demands on mux and register ports.
• Impossible to add multithreading
• Difficult to keep clock cycles.

2).MASSIVE PIPELINING:-

• Five steps:-

1.fetch instrns from m/y

2.read registers and decode instrn.

3.execute instrn or calculate adrs,.

4.access an operand in data m/y.

5.write result to register.

• CAUTIONS ON THE USE OF RISC:

• Code quality should be maintained.
• Scheduling :choose compilers carefully based on quality.
• Debugging:instruction scheduling can make debugging difficult.
• Code expansion
• On chip cache required to feed large instructions.

Posted in: CS,CS 506 Microprocessor Based System Design,Lecture Notes,Semester V