__
·
8087 can be connected with CPU only in
max.mode,i.e wen MN/MX pin is grounded.
·
In max. mode, all control signals are
derived using a bus controller.
·
Multiplexed address-data bus lines are
connected directly from the 8086 to 8087.
·
The status lines and the queue status
lines connected directly from 8086 to 8087.
·
The QS0 and QS1 lines may be directly
connected to corresponding pins in case of 8086/88 based systems.
·
The Request/Grant signal RQ/GT0 of 8087
is connected to
___ __
RQ/GT1 of 8086.
·
The clock pin of 8087 connected with
CPU 8086/88 clock i/p.
·
The interrupt o/p of 8087 is routed to
8086/88 via a programmable interrupt controller.
·
____
·
The pins
AD0-AD15,BHE/S7,RESET,A19/S6-A16/S3 r connected
to corresponding pins of 8086
______
·
BUSY signal 8087 is connected to TEST
pin of 8086.
·
Interrupt o/p INT of the 8087 to NMI
input of 8086. This intimates an error
condition. ______
·
A WAIT instruction is passed to keep
looking at its TEST pin, until it finds pin Low to
indicates that the 8087 has completed the computation.
·
SYNCHRONIZATION must be established
between the processor and coprocessor in
two situations.
a) The execution of an ESC instruction that require the
participation of the NUE
must not be initiated if the NUE has not completed the
execution of the previous
instruction.
b) When a processor instruction accesses a memory
location that is an operand of
a previous co processor instruction .In this case CPU must
synchronize with NPX to
ensure that it has completed its instruction.
Processor WAIT instruction is provided.
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