Minimum
Mode 8086 System
• In
a minimum mode 8086 system, the microprocessor
8086
is operated in minimum mode by strapping its
MN/MX
pin to logic 1.
• In
this mode, all the control signals are given out by the
microprocessor
chip
itself. There is a single
microprocessor
in
the minimum mode system.
• The
remaining components in the system are latches,
transreceivers,
clock
generator, memory and I/O devices.
Some
type of chip selection logic may be required for
selecting
memory
or I/O devices, depending upon the
address
map
of the system.
• The
clock generator generates the clock from the crystal
oscillator
and
then shapes it and divides to make it more
precise
so
that it can be used as an accurate timing
reference
for
the system.
• The
clock generator also synchronizes some external signal
with
the system clock.
• The
working of the minimum mode configuration system
can
be better described in terms of the timing diagrams
rather
than
qualitatively describing the operations.
• The
opcode fetch and read cycles are similar. Hence the
timing
diagram
can be categorized in two parts, the first is
the
timing diagram for read cycle and the second is the
timing
diagram
for write cycle
The
read cycle begins in T1 with the assertion of address
latch
enable (ALE) signal and also M / IO signal. During
the
negative going edge of this signal, the valid address is
latched
on
the local bus.
• The
BHE and A0 signals address low, high or both bytes.
From
T1
to T4, the M/IO signal indicates a memory or I/O operation.
• At
T2, the address is removed from the local bus and is
sent
to the output. The bus is then tristated. The read (RD)
control
signal
is also activated in T2
• The
read (RD) signal causes the address device to enable
its
data bus drivers. After RD goes low, the valid data is available on
the data bus.
• A
write cycle also begins with the assertion of ALE and
the
emission of the address. The M/IO signal is again
asserted
to
indicate a memory or I/O operation. In T2, after sending the
address in T1
the
processor sends the data to be written to the addressed location.
Maximum
Mode 8086 System
• In
the maximum mode, the 8086 is operated by strapping
the
MN/MX pin to ground.
•
In
this mode, the processor derives the status signal S2, S1,S0.
Another
chip
called bus controller derives the control
signal
using
this status information .
• In
the maximum mode, there may be more than one
microprocessor
in
the system configuration.
• The
components in the system are same as in the minimum
mode
system.
• Here
the
only difference between in timing diagram
between
minimum
mode and maximum mode is the status
signals
used
and the available control and advanced
command
signals.
• R0,
S1, S2 are set at the beginning of bus cycle.8288 bus
controller
will
output a pulse as on the ALE and apply a
required
signal
to its DT / R pin during T1.
• In
T2, 8288 will set DEN=1 thus enabling transceivers, and
for
an input it will activate MRDC or IORC. These signals are activated
until T4.
For
an
output, the AMWC or AIOWC is activated from T2to T4
and
MWTC or IOWC is activated from T3to T4.
• The
status bit S0 to S2 remains active until T3 and become passive during
T3 and T4.
• If
reader input is not activated before T3, wait state will be inserted
between T3 and T4.
0 comments:
Post a Comment