DESIGN OF A PC BASED MULTIMICROPROCESSOR SYTEM

Introduction

• Gives an overview of a PC based multimicroprocessor system.
• Designed two subprocessing cards with an 8088 based system &64 memory each.
• These IBM PC compatible cards along with switching logic can be inserted in a PC simultaneously.
• Contain 3 8088 processors with one operating as a master processor while the other two operating in the slave mode.
• Master CPU means the main CPU &slave CPU referred to a subprocessors.
• The job is communicated with the system using the master processor of PC in the form of filenames.
• Master processor checks, if there is any invalid filename in the sequence, if found it accepts the next filename & display the invalid filename
• Both slave processors start executing the program one by one & each slave processor interrupts the main processor to ask for a new job.
• After the execution of each program is over, slave processors store result in respective result memory buffers and master processor store the result in hard disk.
• Hardware design structure describes the design procedure of the module& the details of the subprocessing cards.

Design of the subprocessing units

Design of the address/data separating circuit

• System is built around a PC that has the main processor 8088, acts as a root node/master.
• The main processor & both slave processors address a memory externally interfaced to PC.
• Transreceivers are required to derive the data lines from multiplexed address/data bus the latches are enabled by the ALE signal and the data will be enabled by the DEN signal.DEN signal, combination with DT/R signal decides the direction of data flow.
• ALE, DEN and DT/R are derived by separate 8288 bus controller chip. Since 8088 is used in maximum mode, all control signals are derived by 8288.
• Subprocessors will be able to run only .EXE files. Each subprocessor supports 64K byte memory. There is a constraint that EXE files should not be more than 60K bytes in size. The remaining 4K is reserved for the result buffer of the subprocessor.
• The same 64K memory supported by a slave is interfaced with the CPU of the PC.
• A clock is available at the IO channel of the PC may be used for driving the slave CPUs .There will be the constraint on the slave processors that the maximum speed of their operation can never be more than that of the main CPU.A separate clock generator will add some flexibility of operation and development.
• 64K byte local memory of a subprocessor is to be interfaced such that the subprocessor and the main processor identify a particular location by the same physical address.

Design of the bus window

• Bus window is a part of memory which can be addressed by more than one processor for communication.
• Two slave processors & so there will be two bus windows, one for each. Both windows are addressable by the master processor of PC which is the main processor, but each slave processor can address only one of them.

• The main processor has 64K byte personal memory under 00000 to 9FFFF.The two slots, each of 64K, starting from D0000H to DFFFFH and E0000H to EFFFFH are free. These 64K memory slots can be used as the bus window as well as the local memories for the individual slave CPUs.

To avoid relocation & calculations, identify the memory locations in the window by the same physical addresses for both the processors. This suggests that the memory interfacing logic should be identical for both.

• Main and sub processors able to identify particular location by a single physical address.

Control signals for bus windows

• Here derive read & write control signals for the bus windows.
• As a window is to be written or read by both processors, the MEMR and MEMWR signals of both processors are to be connected to WR and RD pins of memory. A buffer is used for isolating read/write operations of CPU.

Design of isolation between the processors

• When both the processors i.e., slave and master address a common memory, all of their data lines and some of their address lines may be required to be connect with each other.
• When both the CPUs desire to access the common memory concurrently, a conflict may arise due to bus contention among the CPUs .To resolve this conflict, additional hardware is needed which will prevent one processor from referring to the bus window when other processor is using it.
• When one processor is using the bus window, the other one should not be allowed to access the bus, ie. The other processor should not place the address/data on the bus.
• This operation suggests the use of solid state switches .To derive these switches external hardware like address decoders and 8259 I/O cards will be required .The address, data and control lines should be buffered.

Isolation Controllers(Switch Controllers)

1.An 8255 IO Card has been used to control the tristate buffers that provide isolation.

2.When a subprocessor wants to communicate with a bus window,it informs the main processor to disable the tristate buffers.

3.The master C.P.U outputs a '1' bit on the particular pin of the port which is used to drive the chip enable lines of the 74245s which are used for the isolation.

4.Then a reset pin is generated on the another pin of 8255 to reset the slave processor,usin one more OUT instruction,to start the execution.

Interrupt Mechanism

1.As said earlier,the job is transferred to a bus window of a subprocessor for execution.Then a reset pulse is issued to the subprocessor using the OUT operation.

2.The subprocessor starts the execution and when it completes the execution,it shows the halt status on the status lines.

3.From these status lines,a signal is derieved,which interrupts the main processor.

4.The results of execution are next transferred to the master and the slave asks for the next task.

5.After entering the halt state,the status at S_2/,S_1/,S_0/ becomes 011.A signal which is low for all other status and high for the above status is to be generated.A simple 3-input logic will serve the purpose.

6.For any other operation of the processor,the status will be diiferent than that for halt.

7.The o/p of the above given logic,will be high for the above said halt status.

8.Thus, a transition from low to high logic level is achieved,on the interrupt line of P.C.

9.The subprocessor will remain in the halt state,till the main processor allocates it

a new task and resets it 10.After that,it will run the next allocated main task

DERIVING THE REQUIRED CONTROL SIGNAL

• 74245 chips are selected for isolation
• All the 74245s are enabled if the main processor wants to communicate with the bus window
• Signal flow through 74245 is unidirectional
• Enabling or disabling of isolation chips is controlled by isolation driver
• Control line is the RESETIN pin of each 8284A clock generator
• This pin resets when LOGIC 0 is applied to this pin, and the sub processor remains in that state when LOGIC1 is applied to it
• DT/R of PC is not available on the IO channel , it is derived from MEMR and MEMWR signals
• For MEMR operation , the data flows from memory to the CPU, so the isolation buffer is in receiver mode
• For MEMWR operation , data flows from CPU to memory, so the isolation buffer is in transmit mode
• In the diagram of data bus isolation, if DIR pin is high , it enters transmit mode; if it is 0 it enters receive mode
• If the data buffers are enabled at wrong moment then all irrelevant, erratic data present on data bus of the sub processing unit will be placed over the data bus of PC
• Data buffers should be enabled only if any bus window chip is selected
• Main processor sends the isolation control signal through isolation drivers

SYSTEM SOFTWARE DESIGN

System software of the complete system consists of 3 parts:

• Main control program-: controls the total operation of the system

• Two parts are the small local initialisation programs for each sub processors

MAIN PROGRAM DESIGN

• The software for a multiprocessor system should be defined as modular as possible
• Software modules must be used only by a particular processor in its local memory
• The total system is interrupt driven

Complete software is divided into 3 parts:

• MAIN program
• Interrupt routine IRT2 for first sub processing unit
• Interrupt routine IRT3 for second sub processing unit

• The main program accepts the filename inputs at its prompt
• Looks for invalid filename to discard and accepts the next file name
• When sub processer starts execution , the main program makes the master processer to wait for the completion of execution
• Two slave processer use two interrupt inputs of the master to inform it that the previously allotted task is over and the master may read the results and allot them the next task
• Main program consists of two interrupt service routines for the two slaves.
• The functions of them are:

• Store the result of the previous program run by the sub processer
• Select the next program from EXE filename sequence
• Load it to the bus window of that particular sub processer
• Issue run message to the sub processer

• For each of these functions a separate routine is written
• All the routines are linked together to form a complete program
• Each program is checked independently for the passed input parameters
• List of the required inputs to each routine is prepared and checks whether a particular routine prepares the expected output parameters
• This is checked till the complete program run successfully
• Last step is to run the complete program and search for bugs if any and to remove them

MAIN PROGRAM

LOCAL MONITORS

• It contains initialisation routines which initialises the internal registers of the slave processer
• This is for the execution of the allotted task in the local memory
• These programs are available in the local memory and are not accessible to the master

INITIALISATOIN ROUTINE

• When a program is loaded in the bus window of a particular slave processer, the segment registers of that processers should be initialised according to the available local memory

• This routine contains the initialisation of all the segment registers and stack pointers
• After the initialisation of the processer the execution starts from 0200H. This is fixed by the local monitor as the program entry point
• Users program must contain ORG 200H statement at the start of the code segment

Local monitor initialisation program for sub processer1

• Mov AX,0D000H
• Mov DS,AX
• Mov SS,AX
• Mov ES,AX
• Mov SP,0F7FFH
• JMP 0D000:0200H

• For the other sub processer , the same program is used but the segment address of the code and the data segment is 0E000H instead of 0D000H

Posted in: CS,CS 506 Microprocessor Based System Design,Lecture Notes,Semester V